Job Information

Microsoft Corporation Senior Design Verification Engineer in Austin, Texas

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. Join us to achieve this by building the world’s computer. The Artificial Intelligence Silicon Engineering team is seeking passionate, driven, and intellectually curious computer/electrical engineers to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

We are looking for a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.

Responsibilities

In this role you will:

  • Perform pre-silicon verification for complex IP, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

  • Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or SS-level verification.

  • Define verification strategy, requirements, test environments for IP level verification.

  • Create testplans and write tests to provide complete features coverage.

  • Develop and implement technical solutions to complex quality and design challenges.

  • Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.

  • Triage and debug testbench, simulation, and emulation fails.

  • Write makefiles and scripts for verification infrastructure.

  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.

  • Collaborate with teams across sites and geographies.

  • Other

  • Embody our culture and values

Qualifications

Required Qualifications:

  • 7+ years of technical engineering experience

  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 4+ years of technical engineering experience

  • OR Master's degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience

  • OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field

  • 7+ years of experience Technical Engineering with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals.

  • 7+ years of experience and indepth knowledge of verification principles, testbenches, stimulus generation, and UVM based test environments. Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.

  • 7+ years of experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: 

  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

  • 11+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental.

  • 5+ years of experience with scripting language such as Python or Perl or shell scripts.

  • Verification experience for an IP or SS related to CPUs, VPUs, GPUs, Tensor unit, or similar.

  • Knowledge of System Verilog class, constraints, coverage and assertions.

  • Hands-on experience in Formal property verification, formal verification of computational data path designs.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until April 17, 2024.

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .